1. Field of the Invention
This disclosure relates to semiconductor devices and more particularly, to a recess gate-type semiconductor device and a method of manufacturing the same.
2. Description of the Related Art
As semiconductor devices become highly integrated, design rules for semiconductor device components decrease. In particular, for semiconductor devices having many transistors, a gate length, which is a standard of the design rule, decreases. Thus, a channel length of the transistor must also decrease. In addition, the decrease in the channel length results in an increased short channel effect, thus increasing an off-current that is present in the transistors. As a result, the refresh characteristics of a semiconductor device such as a memory device may deteriorate.
In order to overcome this problem, methods of extending the channel length while the gate length remains fixed have been researched. For example, a recess channel may be formed in a semiconductor substrate to form a recess gate or a trench gate.
FIG. 1A is a plan diagram illustrating a conventional recess gate-type semiconductor device. FIG. 1B is a sectional diagram illustrating the conventional recess gate-type semiconductor device taken along line I-I′ of FIG. 1A.
Referring to FIGS. 1A and 1B, the conventional recess gate-type semiconductor device includes an active region 110 defined by a device isolation region 105 formed in a semiconductor substrate, source/drain regions 150 separated from each other in the active region 110, and a gate electrode 130 that is formed between the source/drain regions 150 and that is insulated form the active region 110 by a gate insulating layer 125.
The gate electrode 130 includes a recessed portion 130a that is recessed into the active region 110, and a protruding portion 130b that protrudes from the active region 110. The active region 110 extends in an X1 direction, and the protruding portion 130b of the gate electrode 130 extends in an X2 direction. As illustrated in FIG. 1B, a gate spacer 145 may be disposed on the sidewall of the gate electrode 130.
A channel region surrounds a lower portion of the recessed portion 130a of the gate electrode 130 in the active region 110. As a result, the channel length may be greater than a width L12 of the protruding portion 130b of the gate electrode 130 in the X1 direction. Accordingly, the channel length of the recess gate-type semiconductor device may be greater than the channel length of a planar-type semiconductor device, thereby preventing short channel effects.
However, active core sharpening in the active region 110 occurs at a boundary portion B of the gate electrode 130, because recess trench etching for forming the recessed portion 130a of the gate electrode 130 occurs more slowly at the boundary portion B and thus the corner of the active region 110 is not sufficiently etched.
Therefore, a width L11 of the recessed portion 130a of the gate electrode 130 is less than a width L13 of the protruding portion 130b of the gate electrode 130. As a result, the portion B of the source/drain regions 150 below an edge of the gate protruding portion 130b are formed to a small thickness with low impurity concentration. In other words, the implantation of impurities to form the source/drain regions 150 is obstructed or screened by the edge of the protruding portion 130b of the gate electrode 130 and the spacer 145.
When a gate voltage is applied to the gate electrode 130 of the semiconductor device, an electric field is focused at the portion B of the source/drain regions 150 below the edge of the protruding portion 130b of the gate electrode 130. Accordingly, a junction leakage current of the source/drain regions 150 increases, degrading the refresh characteristics of the semiconductor device, which may be, for example, a memory device.
Embodiments of the invention address these and other disadvantages of the conventional art.